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PBL 403 10 March 2001
PBL 403 10 3.5 V GSM 900 MHz Power Amplifier
Description.
The PBL 40310 is a highly integrated single-ended silicon MMIC power amplifier intended for use in GSM terminals. It delivers 35 dBm at 900 MHz with 55 % power added efficiency into a 50 unbalanced load using a single 3.5 V supply. The circuit has an analog ramp signal to control output power level and a logical on/ off signal for power down mode. It can be used in dual-band amplifiers using the band select logical signal. It can be operated up to 50 % duty cycle with minimum performance degradation. The circuit is housed in a specially designed QSOP16 (150 mil body) package and the implementation requires only few external components. 25 GHz ft state-of-the-art deep trench isolated double-poly silicon bipolar process with additional features for improved wireless performance has been used. On-chip capacitors and inductors are used for the integrated internal matching network. Special front-side metallized substrate contacts provide excellent ground paths from active devices to the highly doped semiconductor substrate and package ground.
Key features.
* * * * * 2.7 to 5.0 V single supply operation 35 dBm output power at 3.5 V 55 % Power Added Efficiency Input matched to 50 Complete on chip input and interstage matching Analog power control Less than 10 A current consumption in power down mode Proven RF Silicon Technology Reliability Minimum number of external components for low overall solution cost
* *
*
V CC
*
RFin
RFout B SEL
Power Control
BIAS
TX - ON
PB
L
3 40
10
Figure 1. Block diagram.
Figure 2. Package outlook.
1
PBL 403 10
Maximum Ratings
Parameter Supply voltage, continuous Power control voltage Input power Operating Case Temperature Storage Temperature Range Conditions Symbol VCC VAPC PIN TOP TSTORAGE -40 -30 Min. -0.5 -0.5 Typ. Max. 6.0 6.0 +20 +85 +100 Unit V V dBm C C
DC Electrical Characteristics
VCC = 3.5 V, TA= + 25C unless otherwise stated. Parameter Supply voltage range Supply current Standby supply current Power down leakage current Input current, VAPC VAPC= 2.5 V, no RF signal applied VAPC<=0.5 V, TX-ON=HIGH VAPC<= 0.5 V, TX-ON=LOW 0 < VAPC < 3.5 V Conditions Symbol VCC ICC ISTBY ILEAK 2.0 Min. 2.7 150 3.0 5.0 3.0 Typ. Max. 5.0 Unit V mA mA A mA
AC Electrical Characteristics
VCC = 3.5 V, fIN = 900 MHz, PIN = 8 dBm, VAPC = 2.5 V, TX-ON = high (VCC), BSEL = low (GND), duty cycle = 12.5 %, pulse width = 577 s, TA = +25C unless otherwise stated. All data measured on evaluation board. Parameter Frequency range Input impedance Input VSWR Recommended input power Power gain Output power Power added efficiency Output power 2 nd harmonic 3 rd harmonic Output Noise Output Noise Forward isolation Stability, load VSWR Ruggedness, load VSWR Power control for max. POUT Power control for min. POUT Power control slope POUT< -30 dBm -10 dBm < POUT< 35 dBm VCC = 2.9 V PIN = 0 dBm PIN = -10 to +20 dBm Conditions Symbol fIN ZIN VSWR PIN GP POUT POUT 2 fo 3 fo 8.0 30 34.5 50 31 35 55 33 tbd tbd tbd tbd -25 VSWR VSWR VAPC VAPC tbd 2.5 0.5 tbd 6:1 10:1 V V dB/V Min. 880 50 2:1 12.0 dBm dB dBm % dBm dBc dBc dBm dBm dB Typ. Max. 915 Unit MHz
RBW=100 kHz, f=925 to 935 MHz RBW=100 kHz, f=925 to 960 MHz VAPC< 0.5 V, PIN = -10 to + 10 dBm All phases, no oscillations. All phases, no damage.
This document contains advance information of a new product. Data given in this document shall be considered as preliminary and may be changed without notice.
2
PBL 403 10
Vcc 1 Vcc 2 GND 3 RFin 4 GND 5 TX-ON 6 BSEL 7 VAPC 8
Figure 3. Pin configuration.
16 15 14 13 12 11 10 9
GND GND GND RFout RFout GND GND GND
Pin Descriptions:
Refer to pin configuration. SO 1 2 3 4 5 6 7 8 Name Vcc Vcc GND RFin GND TX-ON BSEL VAPC Function Supply voltage Supply voltage Common ground RF input Common ground Transmit ON Band select Power control voltage SO 9 10 11 12 13 14 15 16 Name GND GND GND RFout RFout GND GND GND Function Common ground Common ground Common ground RF output RF output Common ground Common ground Common ground
40 35
Pout [dBm], Gain (dB)
80 70 60 50 40 30 Output power (dBm) Gain (dB) Efficiency (%)
RFin V CC
30 25 20 15 10 5 0 -10 -5 0 5 Pin (dBm) 10 15
Eff (%)
1 4
2 12 13 RFout
20 10 0
Power Control
7 8 BIAS 6
B SEL TX-ON
Common ground
Figure 4. RF performance.
Figure 5. Evaluation setup including network for unbalanced input/output.
3
PBL 403 10
Package drawing, QSOP 16
Dim. A A1
D e
millimeters min. max. 1.35 0.10 0.21 0.19 9.80 3.81 0.635mm 5.70 0.41 6.20 1.27 1.75 0.25 0.31 0.25 9.98 3.99
inches min. 0.532 0.004 0.008 0.0075 0.386 0.150
max. 0.688 0.0098 0.012 0.0098 0.393 0.157
B C D E e
E H
0.025 inch ref. 0.2284 0.016 0.2240 0.050
H L
= 0-8 deg.
Pin no 1
B 45 deg.
A A1 C L
Note: This package has been chosen as a preliminary package. It will possibly be changed to a smaller solution.
This document contains advance information of a new product. Data given in this document shall be considered as preliminary and may bechanged without notice.
Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics AB's general conditions of sale, unless otherwise confirmed in writing.
Specifications subject to change without notice. 1522-PBL 403 10 Uen Rev.A (c) Ericsson Microelectronics AB March 2001
Ericsson Microelectronics AB S-164 81 Kista-Stockholm, Sweden Telephone: (08) 757 50 00 www.ericsson.se/microe 4

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